We are seeking an experienced STA (Static Timing Analysis) Engineer to join our team. In this role, you will be responsible for achieving timing closure on high-frequency, congestion-sensitive designs, collaborating closely with the Front-End (FE) team to refine constraints, and working with partition/block owners for ECOs (Engineering Change Orders) to meet timing targets. If you have a solid foundation in advanced timing closure techniques, are experienced with DSM technologies, and possess hands-on expertise with Synopsys or Cadence tools, we encourage you to apply.

Key Responsibilities

1. Timing Closure Expertise. Achieve timing closure for high-frequency designs that are sensitive to timing, congestion, and area constraints.
2. Constraint Development: Collaborate with the Front-End team to develop and clean up design constraints, ensuring seamless integration across the design flow.
3. Engineering Change Orders (ECOs). Partner with partition/block owners to create timing ECOs that facilitate timing closure while maintaining design integrity.
4. Advanced Techniques. Utilize advanced timing closure methodologies to optimize timing paths and meet project requirements.
5. Industry Tools. Apply your knowledge of industry-standard STA tools, particularly those from Synopsys or Cadence, to achieve optimal design outcomes.
6. Deep Submicron Technologies. Work with deep submicron (DSM) technologies, with a preference for candidates experienced with TSMC 5nm processes and below.
7. Scripting and Automation. Leverage strong scripting skills to automate tasks, streamline processes, and enhance overall efficiency.
8. Cross-Functional Collaboration. Communicate effectively with cross-functional teams to address timing challenges and provide regular status updates.

Qualifications

1. Experience. Minimum of 5+ years in STA, with a strong understanding of timing closure, ECO handling, and design constraints.
2. Technical Skills. Proficiency in industry-standard STA tools from Synopsys or Cadence.
3. Advanced Timing Knowledge. In-depth knowledge of timing closure methodologies and strategies.
4. Technology Familiarity. Hands-on experience with DSM technologies, preferably with expertise in TSMC 5nm and below.
5. Scripting Proficiency. Strong skills in scripting languages (e.g., Tcl, Python) for automation.
6. Communication. Excellent verbal and written communication skills for effective team collaboration.

Preferred Skills

• Experience with TSMC 5nm or smaller node technologies.
• Familiarity with advanced timing analysis and closure techniques.
• Demonstrated ability to solve complex timing issues in high-performance designs.

If you're an STA Engineer with a drive to tackle timing challenges in advanced, high-frequency designs, we’d love to hear from you! Join our team to play a key role in the successful delivery of cutting-edge projects.