As a Senior Physical Design Engineer within Microsoft’s Cloud Compute Development Organization (CCDO), you will play a crucial role in developing next-generation silicon hardware for our data centers. This role focuses on the physical design of custom SoCs, from RTL to GDS, ensuring that our silicon designs meet the highest standards of performance, power efficiency, and area optimization.

Key Responsibilities

1. Execution Management. Own the execution of designs from synthesis through place and route, including all signoffs such as timing, physical verification, EMIR, formal equivalence, and low power verification.
2. Floorplanning. Lead the partition floorplanning to optimize blocks for power, performance, and area.
3. Design Issue Resolution. Perform early identification of design flow issues and work with the PD flow/CAD team to address these issues promptly.
4. Collaboration. Partner closely with the RTL team to resolve block closure issues and ensure smooth integration and signoff.
5. Clock Distribution. Implement robust clock distribution solutions that meet design requirements.
6. Technical Trade-offs. Make informed trade-offs between power, area, and timing (PPA) to achieve optimal design outcomes.
7. Mentorship. Mentor junior engineers on technical issues and provide guidance on best practices in physical design.

Qualifications

1. Education. BS/BE/BTech/MS/ME/MTech in Electronics, Microelectronics/VLSI, or Electrical Engineering.
2. Experience. Minimum of 10+ years in semiconductor design with extensive experience in synthesis, floorplanning, place and route, extraction, timing, and physical verification.

Skills

• Proficiency in implementing designs through all stages including synthesis, floorplanning, and signoff.
• Strong understanding of constraints generation, STA, timing optimization, and timing closure.
• Hands-on experience with CTS, global clock distribution, and low power design implementation.
• Expertise in power analysis and optimization methodologies (using tools like PrimePower, PT-PX).
• Familiarity with EDA tools such as Fusion Compiler, Primetime, StarRC, RedHawk, and Formality.
• Experience with automation using scripting languages like Perl, TCL, or Python.

Preferred Qualifications

• Experience with large SoC/CPU/IP design tape-outs in the latest foundry process nodes.
• Excellent project management skills with the ability to handle multiple projects simultaneously.
• Knowledge of IO/Bump planning, RDL routing, formal equivalency checks, reliability, SI, and noise considerations.
• Hands-on experience with PD flows bring-up/setup, and understanding of PD-TFM and methodology.

Security Requirements

• Ability to meet Microsoft’s security screening requirements, including the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Why Join Microsoft?

• Be a part of a leading global technology company and work on cutting-edge projects.
• Collaborate with a team of passionate engineers dedicated to innovation and excellence.
• Enjoy a hybrid work environment that balances flexibility with collaboration.

How to Apply.If you are a seasoned Physical Design Engineer with a passion for cutting-edge technology and meet the qualifications outlined above, we encourage you to apply. Please submit your resume and a cover letter detailing your relevant experience and achievements.